A high level SOPC diagram is shown in the following figure.

The following flow chart illustrates the procedure used to develop SOPC.

Experiment: Control two LEDs on the core board to blink alternatively
Motivation:
1. Understand the procedure used to generate NiosII soft IP core.
2. Understand the procedure used to develop software for NiosII
3. Be familiar with the NiosII IDE
4. Learn the basic software debug methods
5. Learn how to use the PLL module embedded in Cyclone device.
Principle: In this experiment, we will use firmware to control the LEDs to blink alternatively on
the core board.

Steps:

2. Create a new project.
Create a new directory “sopc_led”, create a new QuartusII project named “sopc_led” under the
sopc_led directory. Then create a top level diagram and saved into the created project.

3. Use SOPC Builder to generate NiosII soft IP processor core and peripherals. Click Tools->SOPC
Builder,

Here it is required to specify the system name. In this example, we use niosii_c, and click OK to
enter into SOPC builder:

Select the clock frequency Clock (MHz): in this example, we select 50.00.
Select the target device family: in this example, we select Cyclone II.

On the left panel of the SOPC builder, we can see many different functional modules. Users can
add these modules to the system-to-be-designed.
First, we need to add a CPU, double click NiosII Processor and a NiosII processor-cpu will pop up,
and we select an economical CPU core, i.e., NiosII/e, as following,

Click JTAG Debug Module tab, and select level 1 debug support:

Click Finish to wrap up the configuration of NiosII CPU. A NiosII processor will be added to the
project, and named cpu. For simplicity, we will not change the name. In case you want to
change the name, right click and select ReName, and type in the new name and press ENTER.

Add a RAM as storage device to store data and instruction by double click On-Chip Memory
(RAM or ROM). Memory Type is selected to be RAM; Data Width is 32 bits, Total Memory Size is
4K bytes :

Click Finish to confirm, and return to SOPC builder.

Add a 4-bit PIO port used to control the 4 LEDs by double clicking the PIO(Parallel I/O):

Width is set to 4 bits as following:

Click Finish and return to SOPC builder. Rename the PIO module to led_pio:

The next step is to select System-> Auto-Assign Base Addresses to let system automatically
assign the base address.

The next step is to select System->Auto-Assign IRQs to let system automatically assign interrupt
number. The interrupt number assigned by system is from up to low, and the value is from 0
and increased by 1. The lower the value is, the higher the priority. If user has requirement for
the interrupt priority, it is recommended to manually assign the interrupt number.

Click the newly added CPU module, and select Reset Vector: as onchip_mem, and Exception
Vector: as onchip_mem, as following. Reset Vector determines the starting address when CPU
resets, and Exception Vector set the exception address. Offset value is only used when there are
multiple CPUs. The default works for single CPU system. Click finish when done.

Click System Generation tab, do the final configuration and generate the system.
If simulation is needed, please click Simulation. If not needed, skip it.
Click Generate, and click save to execute the system generation task.

After patiently waiting, the system will report:

Click Exit to quit SOPC Builder.

4. Add the newly created NiosII system to the QuartusII project.

First we need to create a top level diagram:

Double click the blank space on the top level diagram to pop up the Symbol selection window:

5. Add PLL module (If it’s 50MHz, it is not needed, but recommended to add one).
Add a PLL module from the QuatusII libraries to double the frequency of external
clock and feed the CPU.

Click OK and enter into altpll module’s configuration:

Click Next, and set the following:

Click “Input/Lock”:

Click “Output Clocks”:
We only need one clock clk c0 as output. If two clocks are need, click clk c1 or extclk e0, c0 and
c1.

Click “Finish”.

6. Set the compilation settings. Create and run tcl script to assign the pins.

#Setup.tcl 
# Setup pin setting for EP2C5_EP2C8 main board 
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" 
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF 
set_location_assignment PIN_23 -to clk 
set_location_assignment PIN_56 -to reset 
 
 
 
#led 
set_location_assignment PIN_6 -to led\[0\] 
set_location_assignment PIN_5 -to led\[1\] 
set_location_assignment PIN_3 -to led\[2\] 
set_location_assignment PIN_4 -to led\[3\]

7. Compile the project, and download SOF file to FPGA through JTAG. This is to prepare
the hardware system, and to ready for the software debug.

8. Develop the firmware for the project.

Next step is to develop the firmware for the project. Run Nios IDE.

If you are going to use the software directory in the project file we provided. Please read the
following:
We have already prepared the firmware. So in the following, we are going to explain how to
import existing project.

First, we create a directory, workspace, as work space for NiosII IDE.

First, we click the workbench icon and set the workspace directory.

Next step we are going to import the pre-existing project we provided in the project file.

So we import project hello_led_0 and hello_led_0_syslib, both are needed.

Build the project:

For onchip memory, the hex file which is onchip_memory.hex will be placed automatically on
the FPGA QuartusII project directory. When we go back to QII to compile the FPGA, project,
conchip_memory.hex will be compiled into SOF and POF files. In this case, if we program SOF
and POF files, the firmware will be downloaded too. This can only be done for onchip memory. If
use SDRAM or SRAM as storage device, we can only use downloading to flash to store the
firmware.

Debug: Plug USB programmer cable to FPGA core board, and power on. Do Run->Debug As-
>NiosII Hardware:

Switch to debug perspective:

How to change perspective between debug and IDE:

Resume and break point: