Intro

The switch reference design provides a set of board-specific projects.

This design implements a traditional Layer-2 switch at Zynq PL, running without Linux while status can be monitored by u-boot.

Demo runs at u-boot level.

Features

Pre-Built Images

• For quick start demo.

• For image assembling.

• Additional init./config. script.

Block Diagram

Design Outline

Clocks

Resets

The system reset is from Processor System Reset Module and synchronized with the slowest clock, normally the 75MHz PS FCLK1.

Interrupts

Total 4. One interrupts per AXI Ethernet i.e. MAC.

Core Design

Address Map

For Zynq PS address map, please refer to Appx. B of Xilinx UG585.
For MAC register offset and description, please refer to Xilinx PG138.

Demo

• Prepare the images in SD/TF card, or download the pre-built ones.
• Connect two PCs to any two of the four ports, with IPv4 set in the same subnet.
• Configure the registers inside PHY devices for initialization.
  • (For ONS30) vsc8574-setup.tcl should be used.
• Ping each other, should get the response.